For dynamic logic gates, a capacitance is charged during a precharge clock phase and the capacitance is conditionally discharged during an evaluate clock phase, depending on the logical combinational state of logic circuitry. FIG. 1 illustrates a simplified prior art MOS single-rail domino dynamic logic gate. The term "single-rail" means that logical TRUE or FALSE is determined by whether a single evaluation node (110) is high or low. In contrast, dual-rail gates have two evaluation nodes and generalized "mouse-trap" gates may have an arbitrary number of evaluation nodes. The term "domino" means that the gate has an inverting buffer (114) on the output. In FIG. 1, when clock 100 is low (precharge phase), transistor 102 charges the evaluation node capacitance 104 to the supply voltage V.sub.DD. When clock 100 is high (evaluation phase), transistor 106 conditionally discharges the evaluation node capacitance 104 depending on the logical combinational state of logic circuitry 108.
FIGS. 2A and 2B illustrate timing for the dynamic logic circuit of FIG. 1. FIG. 2A illustrates the clock waveform and FIG. 2B illustrates the voltage on node 110. In FIG. 2A, when the clock goes low (precharge state), the voltage on node 110 (FIG. 2B) is driven high. For efficiency, the precharge transistor 102 (FIG. 1) is typically small, sometimes requiring most of the precharge time to charge the node capacitance 104. When the clock goes high (evaluate state), node 110 is high (precharged) and sometime during the evaluate state the node capacitance 104 may be discharged (node 110 pulled low) by the logic circuitry. Note that the evaluation is "monotonic." That is, during the evaluate phase, if node 100 goes low it cannot go high again during the evaluate phase, since once node 110 is discharged the node remains discharged for the duration of the evaluate phase.
Note in particular that the clock 100 inevitably has some jitter, depicted in FIG. 2A where clock 100 has a nominal fall time 200, a worst case late fall time 202 and a worst case early fall time 204. For gates as illustrated in FIG. 1, evaluation must be complete before the worst case early fall time 204 for clock 100. As will be discussed in further detail below, series delay and latching set up times place an additional constraint on evaluation time, requiring evaluation to be complete substantially earlier than the worst case early fall time 204 for clock 100.
In FIG. 1, typically the output 112 is invalid during the entire precharge phase. When dynamic gates are connected as inputs to static logic or to dynamic logic having a different clock phase, the outputs of the dynamic gates typically must be latched to provide valid outputs during the precharge phase. With proper timing and separate delayed clock signals in addition to regular clock signals, some latches may be not be needed, but in general, latches are needed to preserve states during precharge. In addition, latches are needed for test (discussed in more detail below).
FIG. 3A illustrates the logic gate of FIG. 1 with a latch 300 on the output. One common configuration for the output latch 300 is illustrated in FIG. 3B. In FIG. 3B, the transistors forming the inverters 306 and 308 are relatively small so that the output of inverter 306 can be overdriven by inverter 114 (FIG. 3A). In FIG. 3B, with switch 304 conducting, for a low-to-high transition (that is, when logic 108 evaluates to discharge node 110), there is some delay due to the finite resistance of switch 304 followed by additional delay as inverter 306 "fights" to prevent the input 112 from rising. Therefore, the circuit of FIG. 3B adds some delay before the result of an evaluation propagates to downstream logic. An improvement is shown in FIG. 3C. With cross-coupled NOR gates 310 and 312 as illustrated, the clock 100 will go high for the evaluate state substantially earlier than a transition on input 112 resulting from evaluation. Then, input 112 only needs to change the state of a single transistor with no "drive fights." However, there is still some delay. When data is latched after evaluation, the data must be stable for a period of time before the latching clock transition, called a set-up time. For example, for the circuit of FIG. 3B, the data must be stable sufficiently early to permit a delay through switch 304 before clock 100 falls. The latch of FIG. 3C does not have a set-up time requirement. Referring again to the timing diagrams of FIGS. 2A and 2B, in general, evaluation must be complete sufficiently earlier than the worst case early fall time 204 of clock 100 to account for worst case latch set-up time and any series delay between the evaluation node and the latch.
An additional requirement for logic gates is testing. It is common to include circuitry to capture the state of internal circuitry and to bring the captured states out to a test pin where the states are serially read. In addition, test circuitry may be used to control the state of internal circuitry. A commonly used standard for such test circuitry is IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, available from The Institute of Electrical and Electronic Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017-2394. IEEE Std. 1149.1 defines a standard serial interface through which test instructions and test data are communicated. The technique involves the inclusion of a shift-register stage adjacent to each node of interest so that signals at nodes of interest can be controlled and observed. The special shift-registers and test instructions can be used in isolated component testing and in testing individual components assembled into larger systems. In general, there is a need to minimize the overhead of the circuitry required to observe and control internal logic nodes through boundary scan testing. Preferably, instead of additional shift-register stages dedicated to testing, output latches as illustrated in FIG. 3A (300) are also used for boundary scan testing. However, testing typically requires more complex latches than those illustrated in FIGS. 3B and 3C. In particular, the observed output needs to be latched before the output is changed (controlled) by the test system, typically requiring a master/slave latch arrangement. In addition, in FIG. 1, if the clock is stopped, node 110 cannot be controlled if the precharge transistor 102 is on or if the logic evaluates to discharge node 100 and the evaluation transistor 106 is on. Therefore, a bidirectional isolation switch (as in switch 304 of FIG. 3B) is required between node 110 and the node being controlled. An isolation switch adds delay.
There is need for an improved dynamic logic gate with: (1) relaxed timing requirements for the completion of upstream evaluation (2) output holding during the precharge phase, and (3) simplified observability and controllability.